Overview

    Rakun LS1043 system IP block is small foot-print, verified and proven building block consisting of CPU and memory subsystem for easy and inexpensive integration. Complete platform with hardware, Intelectual Property (IP), software and design support.

    It is pre-designed and based on NXP’s LS1043A processor, member of the QorIQ Layerscape 1 family. It features over 15000 CoreMarks of CPU power, 2GB DDR3L memory with ECC, 8GB eMMC memory, DPAA network accelerator, uQE accelerator, 2 10/100/1000 Ethernet PHYs, 4 10Gb/s SerDes Lanes used for SGMII/PCIe/SATA, PWM channels, SPI bus, UARTs etc.

    It is available in the form of PCB layout segment that can be easily integrated into customer specific board. It offers a lot of interfaces, used in telecom and industrial applications. Customization of the system is also available even for smaller quantities. The design supports the dual-core version LS1023A also.

    It runs Linux operating system.

    More Info

    Features

    CPU

    NXP LS1043A CPU, quad Cortex-v8 A53 64bit cores running up to 1.5GHz.

    Quad-core Cortex A53 architecture, delivering over 15000 CoreMarks. 32KB data and 32KB instruction L1 cache per core. 1MB unified L2 cache. Floating point units, NEON co-processor. QorIQ trust architecture.

    QUICC Engine uLite block: 32bit RISC controller, 2 UCCs. Supporting HDLC, TDM, UARTs (PROFIBUS), DPAA Data Path Acceleration Architecture.

    Memory

    Up to 4GB DDR3L memory with ECC. 1600MHz data rate, 32 bit bus. Optional capacities are 256MB, 512MB, 1GB, 2GB and 4GB (4GB commercial temp range only).

    Up to 16GB eMMC flash (8 bit bus).

    32MB QSPI NOR flash. Optional capacities are 4MB to 512MB. It is the default boot memory.

    Connectivity & Peripherals

    Ethernet Interfaces

    • Up to seven 10/100/1000 Mbps Ethernet MACs alltogether, one 10G Ethernet MAC. Max throughput is 15Gbps for 64B packets.
    • Two ports have PHY AR8033 on RGMII, others are available as SGMII, shared with PCIe lanes. IEEE 1588 precision clock synchronization.

    USB Interface

    • Three USB 3.0 Interface with PHY or USB 2.0 OTG interface with PHY.

    SerDes (PCIe/SATA/SGMII)

    • Four SerDes lanes are available. They can be used as as single PCIe x4, dual PCIe x1/2, dual SGMII, single SATA. Availability depends on CPU pinmuxing. SATA 3.0 (up to 6Gb/s) interface.

    Other available interfaces

    CPU’s ports offer a plethora of slower interfaces on its ports thru pinmuxing mechanism. This means that they are not available simultaneously, but are used depending on the application. List of available interfaces:

    • Two full featured UARTs with hardware handshaking (16450/16650 compatible) or four standard UARTs without hardware handshaking (Null-modem). Two additional full featured UARTs with hardware handshaking on QE. PROFIBUS is supported.
    • Six Low Power UARTs
    • Two HDLC interfaces (Synchronous or asynchronous).
    • Two TDM interfaces with up to 128 channels, each running at 64Kbps.
    • Four I2C buses.
    • SPI interface.
    • PWM channels.
    • GPIOs
    Other

    Power Supply

    • 12V or 5V for PoL regulators, 3.3V DC
    • PoL regulators for internal voltages (optionally use your own), brown-out detection and watchdog.
    • Typical power consumption <10W during full operation.
    • Power-save mode.

    Environment

    • Storage: -40ºC to +85ºC
    • Operation: -40ºC to +85ºC
    • Humidity: 5% to 90% Non-Condensing
    • Electrostatic Discharge Tolerance: 2KV
    • Pb free, ROHS compliant

    Approvals

    • CE

    Operating Systems

    • Linux