Borea has opened a new engineering service aimed squarely at the DRAM crisis: redesigning embedded systems onto NXP silicon that customers can actually buy.

The memory market has stopped behaving like a market. Data centre demand has absorbed the bulk of global DRAM output, and equipment makers outside the AI supply chain are being told what they will get rather than ordering what they need. Some OEMs report receiving only half to two-thirds of the volumes they ordered, and SK Hynix has warned the crunch may run past 2030. For an industrial or communications product with a fifteen-year field life, waiting is not a plan.

Borea’s answer draws on the full span of NXP silicon, from PowerQUICC I through QorIQ and Layerscape to the newest i.MX 9 devices. For many products the fastest route back into production is a step backwards — onto a proven older SoC using DDR3, DDR2 or SDRAM in the modest densities that remain sourceable, or that customers already hold in stock. For others it is a step forward, onto an i.MX 9 device that needs a single small LPDDR4 part instead of a high-density array.

What makes the backward step viable is microcode. “When you move to older silicon, the functions that were added in hardware appear to be gone,” says Matevž Langus at Borea. “Usually they are not gone — they were simply moved into silicon later. We can put them back as firmware, in the QUICC Engine, the FMan or the AIOP. The customer loses the memory dependency and keeps the capability.”

The service also addresses a structural problem the shortage has exposed. Products built on third-party CPU modules cannot substitute a memory device, change density or move to an adjacent processor, because the design belongs to the module vendor. Borea’s customers own their designs outright — hardware, software and design data — which is what makes a rapid design-around possible at all.

Borea is an NXP Approved Engineering Consultant and has held NXP microcode development access for QUICC Engine and eRISC/AIOP since 2013.

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Borea has released Rakun X91/X93, a system IP block that lets a single board design run either of two NXP processors.

The block is built around the i.MX 91 and i.MX 93, which are pin-compatible in both the 11×11 mm and 9×9 mm packages and share a PCB layout. A product built on Rakun X91/X93 can therefore be populated with the cost-optimised i.MX 91 or the more capable i.MX 93 — which adds a Cortex-M33 real-time core and an Ethos-U65 NPU — without a respin. The choice can be deferred to the purchase order.

That flexibility has become a supply strategy as much as a product strategy. “Two years ago this would have been a nice-to-have,” says [name, role] at Borea. “Today, being able to switch processors on a board you already have is the difference between shipping and not shipping.”

The memory subsystem was chosen with the same reasoning. Both processors drive a single 16-bit LPDDR4 device, typically 1 GB or 2 GB — a very different part of the market from the high-density DDR4 and DDR5 that data centre demand has drained. Inline ECC is implemented in the processor, so error protection does not require a scarce ECC-specific memory part.

Rakun X91/X93 ships as a PCB layout segment for integration into a customer’s own board, with Linux support and design assistance through bring-up and production. As with all Borea IP blocks, the customer owns the resulting design outright.

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Borea launches world’s first NXP LS1021A based SBC in Qseven form factor. LS1021A is the first CPU from the NXP’s QorIQ family with an ARM core and with addition of graphical interface.
It can be used for various industrial applications where reliability, connectivity and HID is required. Together with Borea’s QuiccEngine microcoding service almost any communication protocol can be supported in the built-in QuiccEngine Communication Processor.

See it in action on Embedded world 2015 Exhibition on EBV booth 5-276 and on Freescale booth 4A-220.

Borea received license to develop custom microcodes for NXP QuiccEngine and eRISC communication processors.