Rakun LS1 system IP block is small foot-print, verified and proven building block consisting of CPU and memory subsystem for easy and inexpensive integration. Complete platform with hardware, Intelectual Property (IP), software and design support.

    It is pre-designed and based on NXP’s LS1021A processor, member of the QorIQ Layerscape 1 family. It features up to 5000 CoreMarks of CPU power, 1GB DDR3L memory with ECC, 1GB NAND Flash memory, 10/100/1000 Ethernet PHY, 4 6Gb/s SerDes Lanes used for SGMII/PCIe/SATA, PWM channels, CAN bus, UARTs etc.

    It is available in the form of PCB layout segment that can be easily integrated into customer specific board. It offers a lot of interfaces, used in telecom and industrial applications. Customization of the system is also available even for smaller quantities.

    It runs Linux operating system.

    More Info



    NXP LS1021A CPU, dual A7 cores running up to 5000 CoreMarks.

    Dual-core Cortex A7 architecture. 32KB data and 32KB instruction L1 cache per core. 521KB unified L2 cache. Floating point units, NEON co-processor. QorIQ trust architecture.

    QUICC Engine uLite block: 32bit RISC controller, 2 UCCs. Supporting HDLC, TDM, UARTs (PROFIBUS).


    1GB DDR3L memory with ECC. 1600MHz data rate, 32 bit bus. Optional capacities are 256MB, 512MB, 2GB and 4GB (commercial temp range only).

    1GB NAND flash (8 bit bus). Hardware accelerated high speed access with ECC support. Optional capacities are 128MB, 256MB, 512MB and 2GB.

    32MB QSPI NOR flash. Optional capacities are 4MB to 512MB. It is the default boot memory. There are two devices on the bus, boot agent can swap them in case of boot failure.

    Connectivity & Peripherals

    Ethernet Interfaces

    • Up to three 10/100/1000 Mbps Ethernet ports, one with PHY AR8033, others are available as SGMII, shared with PCIe lanes. IEEE 1588 precision clock synchronization.

    USB Interface

    • USB 3.0 Interface with PHY or USB 2.0 OTG interface with PHY.

    SerDes (PCIe/SATA/SGMII)

    • Four SerDes lanes are available. They can be used as as single PCIe x4, dual PCIe x1/2, dual SGMII, single SATA. Availability depends on CPU pinmuxing. SATA 3.0 (up to 6Gb/s) interface.

    Other available interfaces

    CPU’s ports offer a plethora of slower interfaces on its ports thru pinmuxing mechanism. This means that they are not available simultaneously, but are used depending on the application. List of available interfaces:

    • Two full featured UARTs with hardware handshaking (16450/16650 compatible) or four standard UARTs without hardware handshaking (Null-modem). Two additional full featured UARTs with hardware handshaking on QE. PROFIBUS is supported.
    • Six Low Power UARTs
    • Four CAN interfaces.
    • Two HDLC interfaces (Synchronous or asynchronous).
    • Two TDM interfaces with up to 128 channels, each running at 64Kbps.
    • Three l2C buses.
    • SPI interface. QuadSPI interface used for boot flash.
    • ESDHC/MMC/eMMC interface
    • PWM channels.
    • I2S, S/PDIF interfaces
    • GPIOs
    • Display controller unit (2D-ACE) 24-bit RGB (12-bit DDR pin interface), up to 2032×2047 pixels max.
    • HDMI transmitter

    Power Supply

    • Single 3.3V DC
    • Regulators for internal voltages (optionally use your own), brown-out detection and watchdog.
    • Typical power consumption <4W during full operation.
    • Power-save mode.


    • Storage: -40ºC to +85ºC
    • Operation: -40ºC to +85ºC
    • Humidity: 5% to 90% Non-Condensing
    • Electrostatic Discharge Tolerance: 2KV
    • Pb free, ROHS compliant


    • CE

    Operating Systems

    • Linux