zobnikSince 2013 we are proud to announce we have become NXP Third Party with access to microcode development for QuiccEngine and eRISC based processors. In addition to using NXP provided microcodes to accelerate network protocol processing we are able to develop entirely custom microcodes that can be downloaded into eRISC enabled NXP chips during run time. We are developing custom eRISC microcodes since 2007.

Custom microcode development usually consists of the following steps:

requirement analysis / specification
hardware modification recommendations to support the microcode
microcode design / development
development of API for the microcode
integration into the OS (by providing standard compliant drivers)
microcode testing
microcode validation/certification, performance testing

We consult what parts of the system could be realised by the dedicated processors (QuiccEngine) in more efficient way than by using the host CPU (Power) or external chips. We treat QuiccEngine enabled parts as multi-core chips, where application must be correctly distributed among all cores (Power and QuiccEngine RISC processors). Micro-code based application approach offers superior multi-core performance compared to simply running SMP Linux kernel on all cores or similar software techniques.

Areas we cover:

system architecture development (putting right things together)
development of customised microcodes
testing of microcodes
integration into other software (operating system)


Main design target for our microcodes is performance. Architecture of the microcode (together with the architecture of the whole system) is designed to be optimal for given application:

adaptation of the microcode to host CPU software: we can adjust microcode to be compatible with existing CPU software or suggest the user how to change CPU software to be faster together with the microcode
adaptation of the microcode to external chips: (we can adjust microcode to be compatible with external chips (for example xDSL line transceivers, …) or suggest different architecture of FPGAs hooked to the QuiccEngine, …

Due to customized microcode design we typically achieve greater than 100% improvement compared to standard microcodes that have been developed for generic market. That is because we target the solution for the application. We can design the microcode from scratch and as such have no dependency on NXP’s code.


Developed microcode is never left “alone” at the user due to the complexity of operation and integration. We provide at least support for integration if not the integration itself. Microcode is integrated into users environment by providing API, demo OS package. We design the microcode as one component in the system, a holistic approach that eases integration, simplifies conformance and reduces time to market. On-site or remote (via the Internet) debugging of the microcode is also provided. This helps us resolve issues in the microcode itself or even help you show the problem in your hardware or the rest of the system. We can for example help your FPGA designer whose FPGA is connected to our microcode to understand the problem in FPGA by tweaking a microcode for testing purposes.


We have designed microcodes utilizing the following protocols so far: IPv4, IPv6, Ethernet, ATM, TDM, VoIP, Realtime/Hard-realtime (UTOPIA, POSPHY).

Microcode references

VSAPC (optimised ATM / AAL5 microcode for CPM) for ADSL access board, together with NXP
PUMA Access Board aggregation microcode for ADSL/VDSL/Fiber Subscriber Access boards in DSLAM packet processing Layer1 – Layer4 with full QoS without using any NXP microcode in QE (running on bare QE)
Implementation of Ethernet, POSPHY and ATM
RTP packet aggregation microcode for VoIP
ITU G.999.1 microcode on QE for next generation DSL chips
Fast UART microcode