When the newest silicon is unobtainable, the fastest route to production is often a step backwards — done properly.
AI infrastructure has swallowed the world’s DRAM capacity. Wafer allocation has moved to HBM and the newest DDR5 densities, and everything else is queuing behind it. For embedded and industrial builders the consequences are brutally practical:
- Lead times that used to be 8 weeks are now measured in tens of weeks, and allocation — not your purchase order — decides your build schedule.
- Prices have moved by multiples, not percentages. In a system where memory is a significant share of BOM value, that alone can destroy a product’s margin.
- Density is the trap. The parts under most pressure are exactly the large, modern, high-density devices that a modern SoC needs to boot at all.
- Redesign is not optional for many teams — it is simply late.
Waiting it out is a strategy only if you can afford to stop shipping. Most of our customers cannot.
Borea redesigns embedded systems onto proven, still-supported NXP processors from one or two generations back — devices whose memory interfaces target DDR3, DDR3L, DDR2 or even SDRAM, in the modest densities that remain sourceable through legacy-focused suppliers, broker channels, or that are very possibly already sitting in your own stock.
This is not a downgrade. It is an engineering trade, and we make it with our eyes open:
- You leave the contested pool. Low-density DDR3L and DDR2 in x16 organisations are built by suppliers who never left the legacy business. That is a different queue from the one everybody else is standing in.
- You need far less of it. An older SoC with a 16- or 32-bit memory bus and a lean, well-optimised software stack does not need gigabytes. Optimisation is our core business — see Optimizations.
- You may already own the parts. Many of our customers discover that the inventory they wrote off as obsolete is now their most valuable asset.
- You get the performance back in software. Where a newer SoC solved a problem in silicon, we can very often solve it in microcode on the older one. This is the part almost nobody else can do — see below.
Borea has been designing with these families since they were current, and has never stopped.
| Family | Typical memory | Status at Borea |
|---|---|---|
| PowerQUICC I (MPC8xx) | SDRAM | Full hardware and software support, CPM microcode |
| PowerQUICC II / II Pro (MPC82xx, MPC83xx) | SDRAM, DDR, DDR2 | Full support, CPM and QUICC Engine microcode |
| PowerQUICC III (MPC85xx) | DDR2, DDR3 | Full support |
| QorIQ P series (P1010, P102x, P2020, P4080 …) | DDR3 | Full support, FMan microcode |
| QorIQ T series (T1023/T1024, T2080, T4240 …) | DDR3, DDR3L, DDR4 | Full support, FMan and QUICC Engine microcode |
| QorIQ Layerscape (LS102xA, LS1043A, LS1046A, LS1028A, LS2088A …) | DDR4 | Full support, AIOP microcode |
| i.MX 6 / 7 / 8 (incl. i.MX6UL, i.MX8M Mini/Nano) | DDR3L, DDR4, LPDDR4 | Full support, proven Rakun IP blocks |
| i.MX 9 (i.MX 91, i.MX 93, i.MX 95) | 16-bit LPDDR4/LPDDR4X, 32-bit LPDDR4X/LPDDR5 | Full support, new Rakun IP blocks — see below |
Because we work across the whole span, we can advise on the move in either direction — and we will tell you honestly when stepping back is the wrong answer for your product.
We also design for footprint compatibility wherever the family allows it. Several NXP families are pin-compatible across variants, and a memory subsystem can be laid out to accept more than one density and more than one supplier. Done at design time, this costs almost nothing. Done in a crisis, it costs a respin.
Stepping back a generation is one answer. It is not the only one, and we will not sell it to you if it is the wrong one.
For a significant class of designs the better escape route is a newer, leaner SoC with a much smaller memory appetite. The i.MX 9 generation is unusually well suited to a constrained market, for a reason that has nothing to do with marketing:
- i.MX 91 and i.MX 93 use a single 16-bit LPDDR4 device. Not an array, not a wide bus, not a DIMM — one small commodity part, typically 1 GB or 2 GB. That is a completely different corner of the market from the high-density DDR4 and DDR5 product the AI build-out has drained, and the choice of qualified suppliers for it is wide.
- Inline ECC comes from the SoC, not from the memory. You get ECC protection on a standard LPDDR4 device, instead of hunting for scarce and expensive ECC-specific parts. For industrial, medical, energy and transport designs this quietly removes one of the hardest lines on the BOM.
- i.MX 91 is pin-compatible with i.MX 93, in both the 11×11 and 9×9 packages, and can run the same PCB layout. One board, two processors, two price and performance points — chosen at purchase order time rather than at design time.
- i.MX 95 gives you a third exit. Its 32-bit interface accepts either LPDDR4X or LPDDR5, so a single design can follow whichever of the two is actually shippable when you build.
- All are covered by NXP’s product longevity programme, which matters when the whole point of the exercise is not to do this again in three years.
Borea now offers proven Rakun system IP blocks for i.MX 91, i.MX 93 and i.MX 95 — the CPU and memory subsystem, already designed, laid out and validated, delivered as a PCB layout segment you drop into your own board. The hardest and riskiest part of an i.MX 9 design, particularly the LPDDR4 layout and power sequencing, is already done and proven in silicon.
- Rakun X91 / X93 system IP block — Cortex-A55 with LPDDR4 and inline ECC, eMMC, dual Gigabit Ethernet, EdgeLock secure enclave, on a layout that accepts either processor. The efficient, long-life workhorse for industrial control, gateways, instrumentation and HMI.
- Rakun X95 system IP block — the six-core Cortex-A55 complex with Cortex-M7 and Cortex-M33 real-time and safety domains, eIQ Neutron NPU, 10 Gigabit and TSN-capable Ethernet. For designs that need edge AI, functional safety or serious networking in one device.
Combined with our microcode and datapath work, this is the same offer as the rest of this page seen from the other side: one partner across the whole NXP span, from MPC8xx to i.MX 95, who can move your design in whichever direction the supply chain actually allows. Very few consultancies are credible at both ends of that range. We have been at both ends continuously since the parts at the old end were new.
The usual objection to older SoCs is software: an ancient vendor BSP, a kernel from a decade ago, no security updates, and no path to compliance.
We remove that objection. Borea backports current Linux kernels to older NXP devices — including PowerPC e300 and e500 cores — and maintains them:
- Current mainline or long-term-support kernel on hardware whose vendor BSP stopped years ago
- Device tree conversion and modernisation of legacy board support
- Current U-Boot, modern toolchains, Yocto or Buildroot integration
- Ongoing CVE tracking and security patching for the lifetime of your product
For European customers this last point is not a nicety. Under the Cyber Resilience Act, a product you continue to place on the market needs a maintained software stack — regardless of how old the silicon underneath it is. An unmaintained 4.x-era vendor kernel is a regulatory problem as much as a technical one. A backported, actively maintained kernel on a well-stocked older SoC is a product you can keep selling.
See also Software design.
Here is where a design-around with Borea stops looking like a compromise.
Newer SoCs are not only faster — they added functions. A protocol accelerator, a timestamping unit, a classification engine, a new interface type. When you step back a generation, those functions appear to be gone.
Very often they are not gone. They are simply not in silicon — and we can put them there in firmware.
Since 2013 Borea has been an NXP Third Party with microcode development access for QUICC Engine and eRISC/AIOP, and we have been writing custom microcodes since 2007. That lets us treat the programmable engines inside these devices as what they really are: soft hardware.
- QUICC Engine and CPM — custom serial protocols, HDLC and TDM variants, deterministic real-time fieldbus and industrial protocols, additional or unusual interface types, precise timing behaviour. → Custom QuiccEngine microcoding
- FMan (Frame Manager) on P and T series — custom parsing, classification, header manipulation and offload for protocols the standard microcode does not know about, keeping wire-rate performance off the cores.
- AIOP on Layerscape — full custom datapath processing. → Custom Layerscape AIOP microcoding
- Multicore datapath programming for everything that belongs above the accelerators. → Multicore datapath programming
The practical result: a function that NXP hardened into a newer chip can frequently be delivered as a downloadable microcode add-on on the older one — removing not just the memory dependency, but sometimes an FPGA or a companion ASIC from your board as well. Our PUMA datapath microcode exists for exactly this reason.
This capability is the core of what we call Extending system possibilities.
Most teams that are stuck right now are stuck for the same reason: somebody else owns their platform.
If your product is built on a third-party CPU module or SOM, then the memory device, the memory density, the SoC variant, the schematic, the bootloader and the BSP all belong to your module vendor. When their memory supply fails, your product fails. You cannot substitute a different DRAM, you cannot drop to a lower density, you cannot move to an adjacent SoC, and you very often cannot even see the schematic that would tell you whether any of it is possible. Your options are to wait, to pay whatever is asked, or to start over.
When you own the design, none of that is true.
- A memory device becomes unobtainable → you qualify a second source, or change density, and respin one layout you already own.
- An SoC goes on allocation → you move within the family, on a footprint you chose to keep compatible.
- A customer demands a new interface or protocol → we add it in microcode, on the board you already have.
- The next shortage arrives → and it will — you are the one holding the schematics, the BOM, the Gerbers and the kernel tree.
Working with Borea, you own your design. The hardware, the software, the design data. We are an engineering partner, not a landlord.
The standard objection to owning your own board is NRE: “we don’t ship enough units to justify a custom design.”
We have spent years making that objection untrue. Borea maintains a library of proven, silicon-validated system IP blocks — the difficult part of any design, already done, tested and manufacturable:
- Rakun LS1 system IP block
- Rakun LS1043 system IP block
- Rakun X6UL system IP block
- Rakun X8MMini/Nano system IP block
- Rakun X91/X93 system IP block
- Rakun X95 system IP block
- i.MX6 customizable embedded design
You start from a working core design and pay only for what is specific to your product. The economics land far below what a full custom development would cost — and the result is still yours, with no per-unit licence attached to it.
See the full hardware IP block portfolio and our hardware products, including the Rakun MPC8306 Industrial SBC and the Lisjak QorIQ high-end gateway platform.
1. Feasibility review (short, fixed scope). We look at what your product actually does, what your current platform actually uses, and what you can actually buy. You get a straight answer: which older SoC and memory configuration fits, what has to move into microcode, what genuinely cannot be carried back, and what it will cost. If the answer is “don’t do this”, we will say so.
2. Architecture and specification. Target SoC and memory selection with real availability data, second-source strategy, footprint compatibility planning, and the software and microcode plan. → System design
3. Hardware. Schematic, layout, signal integrity, prototypes, production support — reusing our IP blocks wherever they fit. → Hardware design
4. Software and microcode. Kernel backport and maintenance, bootloader, drivers, application porting, and any custom QUICC Engine, FMan or AIOP microcode the design needs. → Software design
5. Bring-up, optimisation and support. Making it fast enough on smaller silicon is the fun part. → Optimizations and Embedded Systems Troubleshooting
As an NXP Approved Engineering Consultant, we work with direct access to NXP for QorIQ and i.MX platforms — including on devices most consultancies stopped supporting long ago.
- Your current design is blocked on a DDR4 or DDR5 device you cannot get, or can only get at a price that kills the product.
- You have usable stock of older memory, or older boards, and no engineering capacity to exploit it.
- You depend on a CPU module and your module vendor has just told you what you did not want to hear.
- Your product is a communications, networking, industrial control, transport, energy or instrumentation system with a ten- or twenty-year field life and a demanding real-time or protocol requirement.
- You are running a legacy PowerQUICC or QorIQ design and need it kept alive, secured and extended rather than replaced.
- You need one specific protocol or interface that only exists on a chip you cannot buy.
- You are starting a new design now and want it built on a memory configuration that will still be buyable in 2030 — not one that assumes the market goes back to normal.
Tell us the SoC, the memory part number and the volume, and we will tell you within days whether a design-around is viable and roughly what it takes.
We are not afraid of solving big problems. If your team has stepped into one of those we would be glad to give you a hand there.