Rakun X95 system IP block

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    Overview

    Rakun X95 system IP block

    Rakun X95 system IP block is a small foot-print, verified and proven building block consisting of CPU and memory subsystem for easy and inexpensive integration. Complete platform with hardware, Intellectual Property (IP), software and design support.

    It is pre-designed and based on NXP’s i.MX 95 processor, the high-performance member of the i.MX 9 family. It features a six-core Arm Cortex-A55 complex alongside Cortex-M7 and Cortex-M33 real-time and safety domains, the NXP eIQ Neutron NPU, 3D and 2D graphics, and a 32-bit LPDDR5 or LPDDR4X memory subsystem with inline ECC and inline encryption. Networking is the standout: 10 Gigabit Ethernet plus dual Gigabit Ethernet with TSN, AVB and IEEE 1588 synchronisation.

    It is available in the form of a PCB layout segment that can be easily integrated into a customer specific board. It targets demanding telecom, networking, industrial control, machine vision and transport applications. Customization is available even for smaller quantities. It runs Linux.

    Where it fits

    Rakun X95 is the block to reach for when the application needs more than an efficient Linux controller:

    • Edge AI. The eIQ Neutron NPU with NXP’s eIQ toolchain, alongside an ISP and MIPI-CSI capture for machine vision.
    • Functional safety. i.MX 95 is supported by NXP SafeAssure for ISO 26262 and IEC 61508 programmes, with independent Cortex-M safety and real-time domains.
    • Serious networking. 10GbE plus TSN-capable Gigabit ports and hardware timestamping — for deterministic industrial networking, and for gateway and aggregation products where our multicore datapath programming work pays off.
    • Memory flexibility. The 32-bit interface accepts either LPDDR5 or LPDDR4X. In a volatile memory market, one design that can follow whichever of the two is actually shippable is a real hedge — and inline ECC means you get error protection without a specialised ECC part.

    What you get

    • The validated CPU and memory subsystem as a PCB layout segment
    • The hardest parts of an i.MX 95 design — high-speed LPDDR5/LPDDR4X layout, power sequencing, SerDes routing — already solved and proven
    • Design support through integration, bring-up and production
    • A working Linux platform on day one
    • Full ownership of the resulting design, including hardware, software and design data

    More than a board

    Where the application needs behaviour the silicon does not provide out of the box, Rakun X95 sits inside a wider capability. Borea has been writing custom microcode for NXP communication engines since 2007 and holds NXP microcode development access for QUICC Engine and eRISC/AIOP. Custom datapath and protocol work — see Extending system possibilities — turns a standard platform into one that does exactly what your product needs.

    Related

    Interested?

    Tell us your interface list and your volume and we will tell you what an integration looks like. info@borea.si · Contact us

    More Info

    Processing

    • Up to 6× Arm Cortex-A55 application cores
    • 1× Arm Cortex-M7 real-time core
    • 1× Arm Cortex-M33 safety core
    • NXP eIQ Neutron Neural Processing Unit
    • Arm Mali 3D GPU (OpenGL ES 3.2, Vulkan 1.2, OpenCL 3.0) and 2D GPU
    • NXP ISP for machine vision
    • 1376 kB on-chip SRAM with ECC

    Memory and storage

    • 32-bit LPDDR5 or LPDDR4X up to 6.4 GT/s, with inline ECC and inline encryption
    • [XXX] GB fitted as standard, other densities on request
    • [XXX] GB eMMC 5.1; SD 3.0 / SDIO 3.0
    • Octal SPI, supporting SPI NOR and SPI NAND

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