Borea releases Rakun X95 system IP block for high-performance i.MX 95 designs
Borea has released Rakun X95, a system IP block based on NXP’s i.MX 95 — the company’s highest-performance building block to date and its first with an integrated neural processing unit.
The i.MX 95 pairs up to six Arm Cortex-A55 application cores with independent Cortex-M7 and Cortex-M33 real-time and safety domains, the NXP eIQ Neutron NPU, 3D and 2D graphics and an ISP for machine vision. Networking is the standout for Borea’s traditional customer base: 10 Gigabit Ethernet alongside dual Gigabit ports with TSN, AVB and IEEE 1588 synchronisation.
“This is the part of the i.MX line that has finally caught up with what our communications customers need,” says [name, role] at Borea. “Ten gigabit, TSN, hardware timestamping and a safety island on one device. Previously that meant a QorIQ and a lot of compromises.”
The memory subsystem accepts either LPDDR5 or LPDDR4X on a 32-bit interface, with inline ECC and inline encryption — a deliberate hedge in a market where the availability of any one memory generation cannot be assumed for the life of a product.
Rakun X95 solves the parts of an i.MX 95 design that most often cost a project its schedule: high-speed memory layout, power sequencing and SerDes routing. It ships as a PCB layout segment with Linux support, eIQ machine learning enablement and design assistance through production. NXP SafeAssure support makes it suitable for ISO 26262 and IEC 61508 programmes.